Which is preferred nand or nor

The pull-up and pull-down resistances, now, will be:. To use NOR gate as universal gate either pull up or pull down structure has to be resized decrease the length of PMOS cells or increase length of NMOS cells to have similar resistance as resistance is directly proportional to length length of channel here.

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Thread starter thanuvi Start date May 18, Status Not open for further replies. So NAND layout area is smaller. That makes NAND the universal gate. Teddy Advanced Member level 1. NAND always preferable in terms of logical effort and speed due parallel structure in pull up circuit.

Similar threads E. Which book is better? Gray or Grebene? Started by eco Dec 22, Replies: Which matching technique is better, 1D or 2D? Learn more. Ask Question. Asked 7 years, 6 months ago. Active 3 years ago. Viewed 75k times. According to my understanding delay would be the same. Nick Alexeev Curious Curious 1 1 gold badge 3 3 silver badges 12 12 bronze badges.

It appears that the OP is referring to the internal design of IC's, and not any preference for logic designers to use one or the other, which is what I was mistakenly referring to. Add a comment. Active Oldest Votes. NAND offers less delay. NOR occupies more area. NAND uses transistors of similar sizes. When designing the layout mask, it would be easier if my transistors are of same dimension.

I can make mask by 'copy pasting' or something like that. Time and effort and hence cost can be reduced.